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Synpic12 is an small 12bit RISC meant to be as timing exact as possible, and compatible with the CCS C compiler (12bit) and synthetizable in Actel FPGA devices (at least).

To convert a .hex file to PICROM.vhd please use the included hex2vhdl.py script.

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Release

Date

Package

Source code

Details

REL001

09/05/2011

SynPic12_REL001.zip

SynPic12-REL-001

  • No SLEEP,WDT,TRIS related instructions,  
  • basic tests for complex operations

REL002

13/05/2011

 synpic12-REL002.zip

SynPic12-REL-002

  • Fixed COMF instruction, that made test 13 fail.
  • Added SLEEP instruction (stops, and outs the sleeping signal)
  • Added TRIS instruction (doesn't execute)
  • Automatic test setup on Bamboo + ghdl + python

REL003

*planned*

 

 

  • Include connectors for input/output FIFOs and their status bits
  • Write/Read output signals to access external peripherals

REL004

*planned*

 

 

  • Rom Capable of being implemented in Ram (Actel devices will need preloading)

Bamboo build results feed for the Default build
(This feed is updated whenever the Default build gets built)
S12-DEF-16 was SUCCESSFUL (with 26 tests): <a href="http://projects.nbee.es:8085/browse/S12-DEF-16/commit">Updated by Miguel Angel Ajo</a>

S12-DEF-16 has the following 1 changes:

Miguel Angel Ajo made the following changes at 2011-05-16 01:28:16.983
with the comment: Stack increased to 4,
Ports reduced to 2 (A & B) (freeing more unpaged ram)
Style of signals changed to Wishbone standard.

  • /nbee/ipcores/synpic12/trunk/c/main.sta
  • /nbee/ipcores/synpic12/trunk/hdl/picrom.vhd
  • /nbee/ipcores/synpic12/trunk/hdl/example1.vhd
  • /nbee/ipcores/synpic12/trunk/c/main.c
  • /nbee/ipcores/synpic12/trunk/hdl/picregs.vhd
  • /nbee/ipcores/synpic12/trunk/hdl/pictest.vhd
  • /nbee/ipcores/synpic12/trunk/hdl/PICSTACK.vhd
  • /nbee/ipcores/synpic12/trunk/c/main.pjt
  • /nbee/ipcores/synpic12/trunk/c/main.hex
  • /nbee/ipcores/synpic12/trunk/hdl/picpak.vhd
  • /nbee/ipcores/synpic12/trunk/c/main.bak
  • /nbee/ipcores/synpic12/trunk/hdl/picalu.vhd
  • /nbee/ipcores/synpic12/trunk/hex2vhdl.py
  • /nbee/ipcores/synpic12/trunk/c/main.lst
  • /nbee/ipcores/synpic12/trunk/hdl/synpic12.vhd

The build has 0 failed tests and 26 successful tests.

Workflow

Cell usage for A3P250 device (including a basic C example)

Type

Count

Description

FlipFlops

109

For registers, accumulator, port latches, etc

Gates/muxes/etc

983

Logic control, gate synthetized ROM

RAM (512bit x 18)

1

Registers/internal ram

Example usage

main.vhdl

Synthesis results for A3P250 (including a simple C program compiled in CCS)

Test C code for the core

The test C code executes on our core every time a new version is uploaded into our source respository: http://projects.nbee.es:8085/browse/S12-DEF

http://projects.nbee.es:8060/browse/IPCORES/synpic12/trunk/c/main.c?hb=true

http://projects.nbee.es:8060/browse/IPCORES/synpic12/trunk/hdl/pictest.vhd?hb=true

The C program executes, and for every passed or failed test sends the information out using PORTC (test number) and PORTB (failed/passed).

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